update behav includes

sim/behav/Include/cpu.include

@@ -8,6 +8,10 @@
 ../../src/verilog/cpu/cpu_top.sv
 ../../src/verilog/chip_top.sv
 ../../src/verilog/tb_processor.sv
+../../src/verilog/cpu/control_unit.sv
+../../src/verilog/cpu/decode.sv
+../../src/verilog/cpu/execute.sv
+../../src/verilog/cpu/sign_extend.sv
 
 // you MUST add any new files you make to this include file, follow the path naming above
 // aka '../../src/verilog/cpu/(your module here).sv'