add load stall signal

notes.txt

@@ -0,0 +1,76 @@
+instructions needed (R, I, S, B)
+ops needed:
+  NOP (I)     opcode: 001 0011, funct3: 000                     note: same encoding as addi x0, x0, 0
+  ADD (R)     opcode: 011 0011, funct3: 000, funct7: 000 0000
+  SUB (R)     opcode: 011 0011, funct3: 000, funct7: 010 0000
+  SLL (R)     opcode: 011 0011, funct3: 001, funct7: 000 0000
+  SRL (R)     opcode: 011 0011, funct3: 101, funct7: 000 0000
+  ADDI (I)    opcode: 001 0011, funct3: 000
+  LOAD (I)    opcode: 000 0011, funct3: 010
+  STORE (S)   opcode: 010 0011, funct3: 010
+  BEQ (B)     opcode: 110 0011, funct3: 000
+  EBREAK (I)  opcode: 111 0011, funct3: 000
+
+- opcode [6:0]
+- funct3 [14:12]
+- rs1 [19:15]
+
+R type
+- opcode: 011 0011
+- funct7 [31:25]
+- rs2 [24:20]
+- rs1 [19:15]
+- funct3 [14:12]
+- rd [11:7]
+- opcode [6:0]
+
+I type
+- opcode: 001 0011 | 000 0011
+- imm [31:20]
+- rs1 [19:15]
+- funct3 [14:12]
+- rd [11:7]
+- opcode [6:0]
+
+S type
+- opcode: 010 0011
+- imm [31:25]
+- rs2 [24:20]
+- rs1 [19:15]
+- funct3 [14:12]
+- imm [11:7]
+- opcode [6:0]
+
+B type
+- opcode: 110 0011
+- imm [31:25]
+- rs2 [24:20]
+- rs1 [19:15]
+- funct3 [14:12]
+- imm [11:7]
+- opcode [6:0]
+
+main decoder truth table
+instr     opcode      regwrite      immsrc      alusrc      memwrite      resultsrc     branch      aluop
+add       0110011     1             xx          0           0             0             0           10
+sub       0110011     1             xx          0           0             0             0           10
+sll       0110011     1             xx          0           0             0             0           10
+srl       0110011     1             xx          0           0             0             0           10
+addi      0010011     1             00          1           0             0             0           10
+lw        0000011     1             00          1           0             1             0           00
+sw        0100011     0             01          1           1             x             0           00
+beq       1100011     0             10          0           0             x             1           01
+ebreak    1110011     x             xx          0           0             0             1           01
+
+
+alu decoder truth table
+aluop     funct3      {op[5], funct7[5]}    alucontrol      instruction
+00        x           x                     00 (add)        lw, sw
+01        x           x                     01 (sub)        beq
+10        000         00, 01, 10            00 (add)        add, addi
+          000         11                    01 (sub)        sub
+          001         x                     10 (sll)        sll
+          101         x                     11 (srl)        srl
+
+
+

src/verilog/cpu/control_unit.sv

@@ -8,6 +8,7 @@ module main_decoder (
     output logic [1:0] imm_src_o,  //
     output logic reg_write_o,  // write to register or not
     output logic [1:0] alu_op_o,  // operation for alu to perform
+    output logic load_stall_o,
     output logic instr_invld_o  // invalid or unsupported instruction
 );
 
@@ -20,6 +21,7 @@ module main_decoder (
     mem_write_o = 1'b0;
     alu_src_o = 1'b0;
     alu_op_o = 1'b00;
+    load_stall = 1'b0;
 
     case (opcode_i)
       // lw
@@ -31,6 +33,7 @@ module main_decoder (
         result_src_o = 1'b1;
         branch_o = 1'b0;
         alu_op_o = 2'b00;
+        load_stall = 1'b1;
       end
       // sw
       7'b0100011: begin
@@ -146,6 +149,7 @@ module control_unit (
     output logic [1:0] imm_src_o,
     output logic reg_write_o,
     output logic [1:0] alu_control_o,
+    output logic load_stall_o,
     output logic instr_invld_o,
     output logic ebreak_o
 );
@@ -173,7 +177,8 @@ module control_unit (
       .reg_write_o(reg_write_o),
       .mem_write_o(mem_write_o),
       .alu_op_o(alu_op),
-      .instr_invld_o(instr_invld_md)
+      .instr_invld_o(instr_invld_md),
+      .load_stall_o(load_stall_o)
   );
 
   alu_decoder ad (

src/verilog/cpu/cpu_top.sv

@@ -58,8 +58,9 @@ module cpu_top (
   assign result = result_src ? dsram_rdata_i : alu_result;
 
   logic ebreak_latch;
+  logic load_stall;
 
-  assign stall_core = ebreak_latch | halted_o | ~en_i;  //when else would you stall?
+  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall;  //when else would you stall?
 
   // === Instruction Fetch === //
   // certain ports are tied off bc they depend on modulees you need to implement.
@@ -99,6 +100,7 @@ module cpu_top (
       .imm_ext_o(imm_ext),
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
+      .load_stall_o(load_stall),
       .instr_invld_o(instr_invld_decode),
       .reg_values_o(reg_crossbar_o),
       .ebreak_o(ebreak_latch)

src/verilog/cpu/decode.sv

@@ -14,6 +14,7 @@ module decode (
     output logic [31:0] imm_ext_o,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o,
+    output logic load_stall_o,
     output logic instr_invld_o,
     output logic ebreak_o,
     output logic [31:0] reg_values_o[32]  //Register Values Output
@@ -36,6 +37,7 @@ module decode (
       .imm_src_o(imm_src),
       .reg_write_o(reg_write),
       .alu_control_o(alu_control_o),
+      .load_stall_o(load_stall_o),
       .instr_invld_o(cu_invld),
       .ebreak_o(ebreak_o)
   );