dylan/digital-design-onboarding-F26-main
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remove conflict scaffolding

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Benzi
2026-09-20 19:32:01 -04:00
parent 1d6b45b324
commit 55a0856b5f
2 changed files with 0 additions and 2 deletions
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Makefile
-1
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@@ -80,7 +80,6 @@ submit:
if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \ if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \
echo "Wrote $$submission" echo "Wrote $$submission"
>>>>>>> upstream/main
clean: clean:
$(MAKE) -C sim/behav clean $(MAKE) -C sim/behav clean
$(MAKE) --no-print-directory clean-generated $(MAKE) --no-print-directory clean-generated
src/verilog/cpu/cpu_top.sv
-1
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@@ -5,7 +5,6 @@
// END SYSTEM HEADER // END SYSTEM HEADER
module cpu_top ( module cpu_top (
<<<<<<< HEAD
input logic clk_i, input logic clk_i,
input logic rst_i, input logic rst_i,
input logic en_i, input logic en_i,