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fix instr invld bug

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dylan
2026-09-20 17:47:04 -04:00
parent 4b297b9f0f
commit 729c0dfdc3
1 changed files with 7 additions and 3 deletions
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src/verilog/cpu/control_unit.sv
+7 -3
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@@ -150,14 +150,18 @@ module control_unit (
output logic ebreak_o output logic ebreak_o
); );
logic [6:0] opcode = instr_i[6:0]; logic [6:0] opcode;
logic [2:0] funct3 = instr_i[14:12]; logic [2:0] funct3;
logic funct7 = instr_i[30]; logic funct7;
logic [1:0] alu_op; logic [1:0] alu_op;
logic instr_invld_md; logic instr_invld_md;
logic instr_invld_ad; logic instr_invld_ad;
logic branch_o; logic branch_o;
assign opcode = instr_i[6:0];
assign funct3 = instr_i[14:12];
assign funct7 = instr_i[30];
assign ebreak_o = (opcode == 7'b1110011) && (funct3 == 3'b000) && (instr_i[31:20] == 12'h1); assign ebreak_o = (opcode == 7'b1110011) && (funct3 == 3'b000) && (instr_i[31:20] == 12'h1);
main_decoder md ( main_decoder md (