fix logic assign bugs

src/verilog/cpu/execute.sv

@@ -41,9 +41,11 @@ module execute (
     output logic [31:0] pc_target_o
 );
 
-  logic [31:0] a = rs1_data_i;
-  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data_i;
+  logic [31:0] a;
+  logic [31:0] b;
 
+  assign a = rs1_data_i;
+  assign b = alu_src_i ? imm_ext_i : rs2_data_i;
   assign pc_target_o = current_pc_i + imm_ext_i;
 
   alu alu (