add load stall signal

src/verilog/cpu/decode.sv

@@ -14,6 +14,7 @@ module decode (
     output logic [31:0] imm_ext_o,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o,
+    output logic load_stall_o,
     output logic instr_invld_o,
     output logic ebreak_o,
     output logic [31:0] reg_values_o[32]  //Register Values Output
@@ -36,6 +37,7 @@ module decode (
       .imm_src_o(imm_src),
       .reg_write_o(reg_write),
       .alu_control_o(alu_control_o),
+      .load_stall_o(load_stall_o),
       .instr_invld_o(cu_invld),
       .ebreak_o(ebreak_o)
   );