remove conflict scaffolding

Submit the make submit zip

.gitignore

@@ -9,3 +9,8 @@ __pycache__/
 
 # Cadence/Xcelium simulation output
 sim/behav/WORKSPACE/
+
+# Submission packaging
+*-dd-fall26.zip
+regress.log
+submission.stamp

Makefile

@@ -1,3 +1,12 @@
+# Fill these in before running make submit, for example:
+#   MEMBER_NAME  = George Burdell
+#   GT_USERNAME  = gburdell3
+#   DISCORD_NAME = gburdell67discord
+MEMBER_NAME  =
+GT_USERNAME  =
+DISCORD_NAME =
+export MEMBER_NAME
+
 PYTHON ?= python3
 TEST ?= ebreak
 TEST_DIR := tests/$(TEST)
@@ -6,13 +15,14 @@ CROSSBAR_TIMEOUT ?= 20
 
 TEST_NAMES := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard tests/*/program.asm)))))
 
-.PHONY: help generate smoke test regress clean clean-generated
+.PHONY: help generate smoke test regress submit clean clean-generated
 
 help:
 	@echo "make generate TEST=<name>  Assemble a test and generate golden files"
 	@echo "make smoke                 Test build/TB wiring with a mock DUT"
 	@echo "make test TEST=<name>      Generate and run one RTL test"
 	@echo "make regress               Run every test, print PASS/FAIL summary (logs in tests/<name>/sim.log)"
+	@echo "make submit                Run regress and zip your sources, tests and log for checkoff"
 	@echo "make clean                 Remove generated test and simulator files"
 	@echo "Available tests: $(TEST_NAMES)"
 
@@ -54,6 +64,22 @@ regress:
 		exit 1; \
 	fi
 
+submit:
+	@if [ -z "$(strip $(MEMBER_NAME))" ] || [ -z "$(strip $(GT_USERNAME))" ] || [ -z "$(strip $(DISCORD_NAME))" ]; then \
+		echo "Fill in MEMBER_NAME, GT_USERNAME and DISCORD_NAME at the top of the Makefile first."; \
+		exit 2; \
+	fi
+	@submission="$$(printf '%s' "$$MEMBER_NAME" | tr -d "[:space:]'.,-")-$(strip $(GT_USERNAME))-$(strip $(DISCORD_NAME))-dd-fall26.zip"; \
+	rm -f "$$submission" regress.log submission.stamp; \
+	scripts/sjstamp submission.stamp regress.log src sim/behav/Include tests -- $(MAKE) --no-print-directory regress; \
+	status=$$?; \
+	if [ $$status -eq 125 ]; then echo "Could not stamp the submission, nothing was zipped."; exit 1; fi; \
+	zip -qr "$$submission" src sim/behav/Include tests regress.log submission.stamp \
+		-x '*.DS_Store' 'tests/*/program.o' 'tests/*/program.hex' 'tests/*/sim.log'; \
+	echo "----------------------------------------"; \
+	if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \
+	echo "Wrote $$submission"
+
 clean:
 	$(MAKE) -C sim/behav clean
 	$(MAKE) --no-print-directory clean-generated

README.md

@@ -273,10 +273,12 @@ Disclaimer: We will be running some back end AI and software similarity checkers
 
 In Person Submissions: 
 - We will ask you to walk through the logic and answer a few random questions on must-know concepts. 
+- You still need to run `make submit` and send the zip to the sjcheckoffs Discord Account, same as an online submission. 
 
 Additional Instructions For Online Submissions: 
 - Include a screenshot of all your tests passing with your gt username somewhere in the terminal in the screenshot
-- **submit a zip of the src folder to the sjcheckoffs Discord Account​** <img width="417" height="422" alt="image" src="https://github.gatech.edu/user-attachments/assets/1c271294-ba6a-4314-beb2-e4c76c7e97db" />
+- fill in your name, GT username and Discord username at the top of the `Makefile`, then run `make submit` to run every test and build the zip
+- **submit the zip that `make submit` wrote to the sjcheckoffs Discord Account​** <img width="417" height="422" alt="image" src="https://github.gatech.edu/user-attachments/assets/1c271294-ba6a-4314-beb2-e4c76c7e97db" />
 - Include any supporting documentation you may have used (diagrams, drawings, state machines) 
 
 

src/verilog/cpu/control_unit.sv

@@ -21,7 +21,7 @@ module main_decoder (
     mem_write_o = 1'b0;
     alu_src_o = 1'b0;
     alu_op_o = 1'b00;
-    load_stall = 1'b0;
+    load_stall_o = 1'b0;
 
     case (opcode_i)
       // lw
@@ -33,7 +33,7 @@ module main_decoder (
         result_src_o = 1'b1;
         branch_o = 1'b0;
         alu_op_o = 2'b00;
-        load_stall = 1'b1;
+        load_stall_o = 1'b1;
       end
       // sw
       7'b0100011: begin

src/verilog/cpu/cpu_top.sv

@@ -59,8 +59,24 @@ module cpu_top (
 
   logic ebreak_latch;
   logic load_stall;
+  logic load_stall_cycle;
+  logic load_stall_ff;
 
-  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall;  //when else would you stall?
+  assign load_stall_ff = (load_stall & ~load_stall_cycle);
+
+  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall_ff;
+
+  always_ff @(posedge clk_i) begin
+    if (rst_i) begin
+      halted_o <= 1'b0;
+      load_stall_cycle <= 1'b0;
+    end else if (ebreak_latch) halted_o <= 1'b1;
+    else if (load_stall & ~load_stall_cycle) begin
+      load_stall_cycle <= 1'b1;
+    end else if (load_stall & load_stall_cycle) begin
+      load_stall_cycle <= 1'b0;
+    end
+  end
 
   // === Instruction Fetch === //
   // certain ports are tied off bc they depend on modulees you need to implement.
@@ -101,17 +117,12 @@ module cpu_top (
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
       .load_stall_o(load_stall),
+      .load_stall_ff_i(load_stall_ff),
       .instr_invld_o(instr_invld_decode),
       .reg_values_o(reg_crossbar_o),
       .ebreak_o(ebreak_latch)
   );
 
-  always_ff @(posedge clk_i) begin
-    if (rst_i) halted_o <= 1'b0;
-    else if (ebreak_latch) halted_o <= 1'b1;
-  end
-
-
   always_comb begin
     if (pc_target[31:12] == '0) begin
       branch_vld  = '1;

src/verilog/cpu/decode.sv

@@ -5,6 +5,7 @@ module decode (
     input logic instr_vld_i,  // is instruction passed valid
     input logic alu_zero_i,
     input logic [31:0] rd_data_i,
+    input logic load_stall_ff_i,
 
     output logic pc_src_o,
     output logic result_src_o,
@@ -49,7 +50,7 @@ module decode (
       .rs2_addr_i(instr_i[24:20]),
       .rs1_data_o(rs1_data_o),
       .rs2_data_o(rs2_data_o),
-      .rd_write_en_i(reg_write),
+      .rd_write_en_i(reg_write & ~load_stall_ff_i),
       .rd_addr_i(instr_i[11:7]),
       .rd_data_i(rd_data_i),
       .reg_values_o(reg_values_o)

src/verilog/cpu/fetch.sv

@@ -1,61 +1,61 @@
 //DO NOT MODIFY THIS FILE!
 //DO NOT MODIFY THIS FILE!!
 module fetch (
-    input logic clk_i,
-    input logic rst_i,
-    input logic en_i,
+	input logic clk_i,
+	input logic rst_i,
+	input logic en_i,
 
-    input logic stall_core_i,
-
-    // === Instruction RAM Interface === //
-    output logic isram_en_o,
-    output logic [9:0] isram_addr_o,
-    input logic [31:0] isram_rdata_i,
-    input logic isram_rready_i,
+	input logic stall_core_i,
+	
+	// === Instruction RAM Interface === //
+	output logic isram_en_o,
+	output logic [9:0] isram_addr_o,
+	input logic [31:0] isram_rdata_i,
+	input logic isram_rready_i,
 
 
-    // === Fetched Instruction === //
-    output logic [31:0] instr_o,
-    output logic [31:0] pc_o,  //current instruction
-    output logic instr_vld_o,
+	// === Fetched Instruction === //
+	output logic [31:0] instr_o,
+	output logic [31:0] pc_o, //current instruction 
+	output logic instr_vld_o,
 
-    input logic branch_vld_i,
-    input logic [9:0] branch_trgt_i,
-    input logic branch_taken_i
+	input logic branch_vld_i,
+	input logic [9:0] branch_trgt_i,
+	input logic branch_taken_i
 );
 
 
-  logic [31:0] next_pc;  //instruction to be run at the next cycle
+	logic [31:0] next_pc; //instruction to be run at the next cycle
+	
+	always_ff @(posedge clk_i) begin
+		if(rst_i) begin
+			pc_o <= '0;
+		end else if(en_i & !stall_core_i) begin
+			pc_o <= next_pc;
+		end
+	end
 
-  always_ff @(posedge clk_i) begin
-    if (rst_i) begin
-      pc_o <= '0;
-    end else if (en_i & !stall_core_i) begin
-      pc_o <= next_pc;
-    end
-  end
+	always_comb begin
+		next_pc 	= '0;
+		isram_en_o 	= '0;
+		isram_addr_o	= '0;
+		instr_o 	= '0;
+		instr_vld_o	= '0;
+		if(en_i) begin
+			if (stall_core_i) begin
+				next_pc = pc_o; //when we stall we stay at the same instruction at the next cycle
+			end else if (branch_vld_i && branch_taken_i) begin
+				next_pc = {20'b0, branch_trgt_i, 2'b00};
+			end else begin
+				next_pc = pc_o + 4;
+			end
 
-  always_comb begin
-    next_pc = '0;
-    isram_en_o = '0;
-    isram_addr_o = '0;
-    instr_o = '0;
-    instr_vld_o = '0;
-    if (en_i) begin
-      if (stall_core_i) begin
-        next_pc = pc_o;  //when we stall we stay at the same instruction at the next cycle
-      end else if (branch_vld_i && branch_taken_i) begin
-        next_pc = {20'b0, branch_trgt_i, 2'b00};
-      end else begin
-        next_pc = pc_o + 4;
-      end
+			isram_en_o = 1'b1;
+			isram_addr_o = next_pc[11:2];
+			instr_o = isram_rdata_i;
+			instr_vld_o = isram_rready_i;
 
-      isram_en_o = 1'b1;
-      isram_addr_o = next_pc[11:2];
-      instr_o = isram_rdata_i;
-      instr_vld_o = isram_rready_i;
-
-    end
-  end
+		end
+	end
 
 endmodule

src/verilog/cpu/reg_file.sv

@@ -1,45 +1,46 @@
 // 32 x 32-bit RISC-V integer register file.
 // Register x0 always reads as zero and ignores writes.
 module reg_file (
-    input logic clk_i,
-    input logic rst_i,
+    input  logic        clk_i,
+    input  logic        rst_i,
 
-    input  logic [ 4:0] rs1_addr_i,  //Register Source 1 Address Input
-    input  logic [ 4:0] rs2_addr_i,
+    input  logic [4:0]  rs1_addr_i, //Register Source 1 Address Input
+    input  logic [4:0]  rs2_addr_i,
     output logic [31:0] rs1_data_o,
-    output logic [31:0] rs2_data_o,  //Register Source 2 Data Output
+    output logic [31:0] rs2_data_o, //Register Source 2 Data Output
 
-    input logic        rd_write_en_i,  //Register Destination Write Enable Input
-    input logic [ 4:0] rd_addr_i,
-    input logic [31:0] rd_data_i,
+    input  logic        rd_write_en_i, //Register Destination Write Enable Input
+    input  logic [4:0]  rd_addr_i,
+    input  logic [31:0] rd_data_i,
 
     // Read-only architectural state exposed to the debug crossbar.
-    output logic [31:0] reg_values_o[32]  //Register Values Output
+    output logic [31:0] reg_values_o [0:31] //Register Values Output
 );
 
-  logic [31:0] registers[32];
-  integer i;  //used for generate loops in systemverilog
+    logic [31:0] registers [0:31];
+    integer i; //used for generate loops in systemverilog
 
-  always_comb begin
-    rs1_data_o = (rs1_addr_i == 5'd0) ? 32'd0 : registers[rs1_addr_i];
-    rs2_data_o = (rs2_addr_i == 5'd0) ? 32'd0 : registers[rs2_addr_i];
-  end
-
-  assign reg_values_o[0] = 32'd0;
-  generate
-    for (
-        genvar register_index = 1; register_index < 32; register_index++
-    ) begin : gen_debug_register_values
-      assign reg_values_o[register_index] = registers[register_index];
+    always_comb begin
+        rs1_data_o = (rs1_addr_i == 5'd0) ? 32'd0 : registers[rs1_addr_i];
+        rs2_data_o = (rs2_addr_i == 5'd0) ? 32'd0 : registers[rs2_addr_i];
     end
-  endgenerate
 
-  always_ff @(posedge clk_i) begin
-    if (rst_i) begin
-      for (i = 0; i < 32; i = i + 1) registers[i] <= 32'd0;
-    end else if (rd_write_en_i && (rd_addr_i != 5'd0)) begin
-      registers[rd_addr_i] <= rd_data_i;
+    assign reg_values_o[0] = 32'd0;
+    generate
+        for (genvar register_index = 1;
+             register_index < 32;
+             register_index++) begin : gen_debug_register_values
+            assign reg_values_o[register_index] = registers[register_index];
+        end
+    endgenerate
+
+    always_ff @(posedge clk_i) begin
+        if (rst_i) begin
+            for (i = 0; i < 32; i = i + 1)
+                registers[i] <= 32'd0;
+        end else if (rd_write_en_i && (rd_addr_i != 5'd0)) begin
+            registers[rd_addr_i] <= rd_data_i;
+        end
     end
-  end
 
 endmodule

src/verilog/sram_wrapper.sv

@@ -4,46 +4,46 @@
 //DO NOT MODIFY//
 module sram_wrapper (
     input  logic        clk_i,
-    input  logic        rst_i,
+    input  logic        rst_i,	
     input  logic        en_i,
     input  logic        write_en_i,
-    input  logic [ 9:0] addr_i,
+    input  logic [9:0]  addr_i,
     input  logic [31:0] wdata_i,
     output logic [31:0] rdata_o,
-    output logic        rready_o
+    output logic 	rready_o
 );
 
-  CF_SRAM_1024x32_macro u_sram (
-      .DO       (rdata_o),
-      .DI       (wdata_i),
-      .AD       (addr_i),
-      .CLKin    (clk_i),
-      .EN       (en_i),
-      .R_WB     (~write_en_i),
-      .BEN      (32'hFFFF_FFFF),
-      .TM       (1'b0),
-      .SM       (1'b0),
-      .WLBI     (1'b0),
-      .WLOFF    (1'b0),
-      .ScanInCC (1'b0),
-      .ScanInDL (1'b0),
-      .ScanInDR (1'b0),
-      .ScanOutCC(),
-      .vpwrac   (1'b1),
-      .vpwrpc   (1'b1)
-  );
+    	CF_SRAM_1024x32_macro u_sram (
+    	    .DO        (rdata_o),
+    	    .DI        (wdata_i),
+    	    .AD        (addr_i),
+    	    .CLKin     (clk_i),
+    	    .EN        (en_i),
+    	    .R_WB      (~write_en_i),
+    	    .BEN       (32'hFFFF_FFFF),
+    	    .TM        (1'b0),
+    	    .SM        (1'b0),
+    	    .WLBI      (1'b0),
+    	    .WLOFF     (1'b0),
+    	    .ScanInCC  (1'b0),
+    	    .ScanInDL  (1'b0),
+    	    .ScanInDR  (1'b0),
+    	    .ScanOutCC (),
+    	    .vpwrac    (1'b1),
+    	    .vpwrpc    (1'b1)
+    	);
+	
 
+	logic rdata_valid;
 
-  logic rdata_valid;
+	always_ff @(posedge clk_i) begin
+		if(rst_i) begin
+			rdata_valid <= 1'b0;
+		end else begin
+			rdata_valid <= en_i;
+		end
+	end
 
-  always_ff @(posedge clk_i) begin
-    if (rst_i) begin
-      rdata_valid <= 1'b0;
-    end else begin
-      rdata_valid <= en_i;
-    end
-  end
-
-  assign rready_o = rdata_valid;
+	assign rready_o = rdata_valid;
 
 endmodule